Compiler detected instruction level parallelism

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These arguments bring out a basic point - compiler detected instruction level parallelism also requires dynamic scheduling support within the processor .ILP Introduction, Compiler Techniques and Branch. Prediction. – 3.1, 3.2, 3.3 Dynamic RAW hazard detection and scheduling in data-flow fashion. Detecting dependence of registers is straightforward. Register names are fixed in the instructions. Dependences that flow through memory locations are more How can we exploit ILP at run time? • Minimal hardware support (w/ compiler support). • Dynamic OOO (out-of-order) execution support. ILP Introduction, Compiler Techniques and Branch. Prediction. – 3.1, 3.2, 3.3 Dynamic RAW hazard detection and scheduling in data-flow fashion. Compiler techniques for exposing ILP: Pipeline scheduling, Static approaches > compiler-based is detected and if it is s causes a “stall.”. ILP and Data Hazards prevented interesting compiler scheduling of operations (1) the distribution of the hazard detection logic.