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This paper compares Cortex-R4 and Cortex-M3(M4 has additional DSP over M3). It does not compare about 6 Instruction Set Architecture. Cortex-R has ARM, The five versions of the ARM instruction set architecture to date are as follows: M0, M1, M2, M3, and M4 (M[4:0]) are the mode bits, and these determineSingle Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 and Cortex-M7 cores to simplify development of application software. SIMD Cortex-M4 Processor Features. • 32-bit Reduced Instruction Set Computing (RISC) processor. • Harvard architecture. – Separated data bus and instruction bus. ARM Cortex-M4 Processor Instruction Set. – ARM and Thumb Instruction Set. – Cortex-M4 Instruction Set. 1.LiB Low-level Embedded NXP LPC4088 Quick Start. This manual contains documentation for the. Cortex-M4 processor, the programmer's model, instruction set, registers, memory map,floating point, multimedia, Table 7.1. FPU instruction set. Operation, Description, Assembler, Cycles. Absolute value, of float, VABS.F 32, 1. Addition, floating point, VADD.F 32, 1. The processor implements the ARMv7-M Thumb instruction set. Table 3.1 shows the Cortex-M4 instructions and their cycle counts. The cycle counts are based on