Addps instruction

endbr32 instructionvmulps
vmovups instruction
x64 assembly instruction set
addss
shufps
vaddps
in instruction x86

ADDPD, Add Packed Double-Precision Floating-Point Values. ADDPS, Add Packed Single-Precision Floating-Point Values UD2, Undefined Instruction. Opcode/Instruction, Op / En, 64/32 bit Mode Support, CPUID Feature Flag, Description. NP 0F 58 /r ADDPS xmm1, xmm2/m128 4.4.1 ADDPS Instruction ADDPS (diregidisrc KMM); *** P3, P4, ATHLONXP NASM ADDPS XMMreg, r/m128 Add packed single-precision floating point.x86 Instruction Set Reference. ADDPS 0F 58 /r, ADDPS xmm1, xmm2/m128, Add packed single-precision floating-point values from xmm2/m128 to xmm1. ADDPS—Add Packed Single-Precision Floating-Point Values. INSTRUCTION SET REFERENCE, A-L. 3-36 Vol. 2A Instruction Operand Encoding. Description. SSE stands for Streaming SIMD Extensions. It is essentially the floating-point equivalent of the MMX instructions. The SSE registers are 128 bits, addps. ADDPS. add packed single-precision floating-point values. addss. ADDSS. add scalar single-precision floating-point values. All the SSE instructions (listed below) scale out to parallel execution, SIMD style. So "addss" adds one float, "addps" adds four floats, SIMD style.