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Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. 3.1a refers to the Accellera SystemVerilog 3.1a Language Reference Manual [B4], Updated Feb 26, 2018: IEEE releases 1800-2017 Standard.. Today at this week's DVCon IEEE Standard for Verilog/SystemVerilog Language Reference Manual. IEEE 1800-2017: SystemVerilog (SV) · IEEE 1800.2-2017: Universal Verification IEEE 1076: VHDL Language Reference Manual · IEEE 1450.6.1: Open