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The Ml machine cycle is always a memory read op-code fetch. The CPU can perform only one activity at a time and only one control line can thus be active at any given instant. A single microprocessor instruction may require several bytes and several machine cycles; the Intel and Zilog processors studied in this book have a maximum of four bytes per instruction and six machine cycles per instruction.

Instruction Timing. The mnemonics are listed in alphabetical order followed by a brief description of the instruction. The binary equivalent of the op-code is also given. The chart also includes the number of clock cycles—sometimes called T states— required for each instruction. From this information we can conclude that the program given in Fig. If the microcomputer system clock is 2. The important point to remember is that not all machine cycles are of equal length even though Fig.

Processor Timing. Each T state is identified as one pulse from the system Sec. HAL 10 1. Instruction set of the microprocessor. Courtesy of Intel Corporation. Introduction to the Microprocessor clock. In this instance both machine cycles are shown as three T states long, but this may not always be true. Rather than try to show 16 separate lines for the address bus, it is shown as two parallel lines symbolizing that some of the lines are a logic 1 level and some a logic 0 level.

When these lines cross, a new address is output by the CPU. Similarly, the eight lines of the data bus are defined only when valid data is present and left unknown elsewhere.

Examining the memory read machine cycle in Fig. The memory unit now has the time until the falling edge of the clock during the T3 cycle to find the data requested by the CPU and place it on the data bus. This time is referred to as the access time of the memory. Notice that the data bus is expected to receive valid data from the memory when the falling edge of T3 occurs, and at no other time during this machine cycle is data valid on the bus.

The memory write cycle is similar to the memory read cycle except that the processor now outputs the data instead of the memory unit.

To give the memory plenty of time to latch the data, the data bus contains valid data early in the machine cycle. The CPU is hard-wired to follow continually the sequence: fetch an operation code from memory, increment the program counter, execute the instruction. In binary an individual digit is called a bit and a group of 8 bits is referred to as a byte. The hexadecimal number system provides a convenient means of expressing binary numbers. Programming the computer by supplying the instruction operations in hex or binary is called machine language programming.

A mnemonic is an abbreviation for a computer instruction that suggests the intent of that instruction. Supplying the microcomputer with mnemonics is called assembly language programming.

Digital signals switch between logic 1 and 0 levels. Most microcomputer systems use TTL logic circuits in which a logic 1 is a voltage greater than or equal to 2. The typical 8-bit microprocessor with bit address bus can access 65, 8-bit memory locations. This is referred to as 64K of memory space. The time to execute a microcomputer program can be found by adding up the total clock cycles or T states required for all instructions in the program.

Modify this program so that it will accept decimal numbers as large as 65,, convert to a bit binary number, and print the result. Using this function, modify the program of Lab 1. If a key keypad is unavailable, two 8-switch DIP switches can be substituted. Which are bidirectional? Because this random data cannot be executed with predictable results, the computer is not usable.

Section 1. What happens to this memory capacity when one additional memory line is added? State the general result for adding n additional memory lines. Express your answer in hex and in decimal.

This is found by complementing all bits and adding 1. Positive numbers are left unchanged. If the MSB is a 1, a negative number is indicated see Table 1. Following these rules, convert the following 8-bit signed numbers to decimal. What is the reasoning behind this? Which version will have the shortest execution time? Which one do you think is the easiest to write? Explain why. If keys 4 and 5 are both held down, what is the binary output code that will be produced?

Refer to Fig. Assume the connection between EO and El of the two encoders breaks open. What would the symptom of this problem be? Hint: TTL circuits interpret open pins as logic Is. How many address lines would be required to access all locations in this memory? What is the hexadecimal address corresponding to decimal page 48 line ? What is the hex address of the last byte in this memory? Indicate the starting address of each block. Assume that such a circuit is used to test a microprocessor and that the data bus lines are measured with a voltmeter.

What operation code does it represent as an microprocessor instruction? How many total bytes does this program require? How will the CPU interpret this byte when the program is run?

Follow the format shown in Fig. Referring to Fig. We begin this task by forming the basic CPU module for each chip. This module will be consistent with the definition of the CPU presented in Chap. The chapter concludes with an introduction to the instruction sets of the three processors, a discussion of addressing modes, and a sample program written in assembly language with hexadecimal instruction codes. List two different design techniques commonly used to build a microcomputer system.

As discussed in Chap. This technique is shown in Fig. This type of microcomputer design is referred to as bus-oriented because all of the parallel connectors form a common bus. But if this bus is to be truly useful, everyone must agree on the signal definitions for each pin of the bus.

All told, pins are specified, including three power supply voltages, a system clock signal, numerous control signals, and the address and data bus lines. The maih advantage of a bus-oriented computer is flexibility.

Indeed, it is even possible to change the CPU board and operate with an entirely new microprocessor. With the advances in integrated-circuit technology, it has become possible to construct the entire computer on a single board. An example of a single-board computer SBC is shown in Fig. The advantage to this technique is the compact design that results and low cost.

The CPU Module. In this chapter we are concerned primarily with the CPU portion of the microcomputer system. This module must generate a system clock signal and Figure 2. This photo illustrates an S standard pin connector computer. The disk drives and power supply are in the right-hand compartment.

Courtesy of North Star Computers. Courtesy of Zilog, Inc. In most cases this means that several TTL packages will be required to support the microprocessor as the CPU module is assembled. As you can see, several ICs are required in addition to the microprocessor chip itself the long pin device in the figure. In the next section we begin to detail the requirements for practical CPU modules for the , , and Z microprocessors. The first samples of the became available in December , so it is not a new device.

Figure 2. The does not directly provide the control bus signals we are familiar with from Chap. Instead, it provides a SYNC signal that pulses high during the first T cycle of each Ml machine cycle that is, the first clock pulse of each instruction 36 Chap. Ao is the least significant address bit. Also, during the first clock cycle of each machine cycle, the A outputs a status word on the data bus that describes the current machine cycle.

Do is the least significant bit. The HOLD state allows an external device to gain control of the A address and data bus as soon as the A has completed its use of these busses for the current machine cycle. In either case, the HLDA signal appears after the rising edge of 2. It is automatically reset disabling further interrupts at time T1 of the instruction fetch cycle Ml when an interrupt is accepted and is also reset by the RESETsignal.

Note that the flags, accumulator, stack pointer, and registers are not cleared. VSS Ground: Reference. The clock levels are not TTL compatible. When SYNC is high, the data bus carries status information that may be latched and decoded to provide a control bus. Table 2. Example 2. Studying Fig. Referring to the status word chart in Table 2. This is shown in Fig. The other three control signals are developed in a similar manner.

Indicates that the address bus holds the pushdown stack address from the Stack Pointer. Indicates that the address bus contains the address of an output device and the data bus will contain the output data when WR is active.

The status word tells us what is about to happen that is, the type of machine cycle , but DBIN and WR tell us that the microprocessor is now ready to make it happen. Because the status bits disappear after the T2 state, they must be latched until needed. There is more information in the status word than is absolutely necessary for developing the control bus signals.

For example, it is possible to distinguish between three types of memory reads—an instruction fetch, a memory read, and a stack read—by decoding status words 1, 2, and 4. Usually, this is not done and only the decoding shown in Fig. If you are beginning to picture the as a rather complex chip to interface, you are correct. To make this job simpler, Intel has provided two support devices for the the system controller and the system clock generator.

With these two chips we can finally draw the CPU module for an based microcomputer. The develops the two-phase clock signal from an external crystal. It divides the crystal frequency by 9, forms the two clock phases, and level-shifts the waveforms to the MOS levels required by the It also provides a TTL-level clock signal that may be used by other circuits in the Sec. Because of the divide-by-9 feature, a typical A crystal is 18 MHz, resulting in a 2-MHz system clock. The third chip in the CPU module is the This circuit takes the place of the latch and decoder circuitry shown in Fig.

In addition, it buffers amplifies the data bus lines so they will not be loaded down by the many chips connected to this bus. In summary, the is actually a three-chip CPU module requiring the clock generator and the system controller.

An external crystal determines the system clock frequency. A few lines remain to be explained in Fig. As the state of the art in semiconductor technology advanced, it became possible for Intel to redesign the and include the and in a single package.

The result is the microprocessor. Although there are several differences when compared with the older , the most important similarity is that the is object code-compatible with the This means that all software written for the will also run on the without any changes. Most manufacturers have settled on the pin package as a good compromise between a component that can be readily handled without breakage and "still provide many lines of access to the chip itself.

This is what the designers of the chose to do. They maintained the standard pin package but combined the low-order address lines AO through A7 with the data bus lines DO through D7. For this scheme to work a new signal is required to identify when AD0-AD7 represent data and when they represent the low-order address.

Intel calls this line ALE for address latch enable. The most significant differences when compared with the can be summarized as follows: 1.

The clock signal is generated internally from an external crystal or RC network connected to XI and X2. The internal clock runs at one-half the oscillation frequency of this circuit. The signal ALE is used to distinguish between the two. Notice that ALE pulses high during the T1 clock pulse of each machine cycle. The latch is used to demultiplex AD0-AD7.

The gating array is used to form a control bus consistent with the CPU module. When these devices are used, the becomes a single-chip CPU module. What has been gained by this multiplexing scheme? Several new interrupt inputs special inputs to the microprocessor causing it to suspend its present task temporarily have been provided giving the considerably more flexibility than the when servicing interrupts.

Finally, Sec. The falling edge of ALE can also be used to strobe the status information. So and Si become valid at the beginning of a machine cycle and remain stable throughout the cycle.

The falling edge of ALE may be used to latch the state of these lines. Data is set up at the trailing edge of WR. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods.

The input frequency is divided by 2 to give the processor's internal operating frequency. The period of CLK is twice the X,. READY must conform to specified setup and hold times. The processor can regain the bus only after the HOLD is removed.

It is unaffected by any mask or Interrupt Enable. See Table 2. The INTR is enabled and disabled by software. It can be used to activate an A Interrupt chip or some other interrupt port. RST 5. The priority of these interrupts is ordered as shown in Table 2. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Because SO and SI are output early in the machine cycle, they can be used to generate early read and write control signals.

This technique is useful for increasing memory access times allowed by the processor and allowing slower memory parts to be interfaced. In summary, the is software-compatible with the , includes an onchip clock oscillator, requires an external latch for interfacing standard memories, and will require some simple gating to generate compatible control bus signals.

In fact, Zilog is fond of calling the a subset of the Z Of course, Intel considers the to be its version of an enhanced Although neither the nor the Z are pin-compatible with the , the Z more closely resembles the CPU module than does the The 46 Chap.

Sh Output, active low. During reset time, the address and data bus go to a high impedance state and all control output signals go to the inactive state. Bus acknowledge is used to indicate to the requesting device that the CPU address bus, data bus and tri-state control bus signals have been set to their high impedance state and the external device can now control these signals. Aq-A 5 constitute a bit address bus. Dq- D7 constitute an 8-bit bidirectional data bus.

M Machine Cycle one Output, active low. M indicates that the current machine cycle is the OP code fetch cycle of an instruction execution. The memory request signal indicates that the address bus holds a valid address for a memory read or memory write operation. An IORQ signal is also generated when an interrupt is being acknowledged to indicate that an interrupt response vector can be placed on the data bus. Tri-state output, active low.

Z also goes a step beyond the in that it is not only object code-compatible but has a greatly expanded instruction set when compared with the Indeed, some people feel that the instruction set is too complicated. You can judge this for yourself later in the chapter when the instruction sets of the three processors are presented. Unlike the , the clock signal must be generated external to the chip, but unlike the , it is a single-phase TTL-compatible signal.

A typical clock frequency for the Z is 4 MHz. Also unlike the , but similar to the , the address and data buses are not multiplexed. Basic system timing for an op-code fetch machine cycle is shown in Fig.

One of the more notable features of the Z is the refresh address output on A0 through A7 during T3 and T4 of each Ml machine cycle. This is discussed in more detail in Chap.

Again a simple gating array is required to produce an like control bus. We study this in more detail in Chaps. Finally, there are several other control-oriented signals not shown in the CPU module. These are dealt with later when the subjects of interrupts and DMA Chap. In summary, the Z is an enhanced in a single IC package. Its bus structure is rrfore straightforward than either the or the It does require an external clock generator, but this can be a simple 74LSbased crystal oscillator.

Which CPU register stores the address of the next instruction to be fetched and executed? An understanding of the CPU module is essential when your goal is to design and construct a particular microcomputer system. However, when the goal is to develop software for a particular processor that is, control and applications programs , a knowledge of the CPU module is less important.

For example, to write an assembly language program we do not need to know how the clock signal is generated or that status information is output at the beginning of each machine cycle. What we do need is a knowledge of the inner workings of the microprocessor itself. This information is usually presented in the form of a programming model.

The programming model is a diagram of the internal registers and flags within the CPU. Recall that we have already seen one special register in Chap. In general, a register is a storage location in the CPU. The accumulator is special because data in this register can be manipulated mathematically or logically.

The nonaccumulator registers are called general-purpose registers and can be used to store temporary information recall how the B register was used for temporary storage in the addition problem in Sec. Once these models are understood, we will be able to make efficient use of the instruction sets of the processors and begin to write assembly language programs. A Programming Model for the The has six 8-bit general-purpose registers called Sec. The A register is the accumulator and register F is a special flag register.

There are also two bit registers labeled register SP and register PC. Register PC is the program counter and its bit length is consistent with the bit address bus of the As mentioned in Chap. Register SP is called the stack pointer register. It also holds a bit address, but this address is interpreted as pointing to a special section of memory called the stack. The stack area of memory can be used to supply a nearly unlimited number of general-purpose registers external to the microprocessor.

It is also used to save the return address when a subroutine call instruction is given. We will learn more about the stack later in this chapter. Recall that all data for the is 8 bits in length. Therefore, when the CPU fetches an instruction from memory, it will issue a bit address, but it will retrieve only 8 bits or one byte of data. The general-purpose registers are intended for storing data bytes, but the stack pointer and program counter registers are used to specify memory locations or addresses.

Some of the instructions allow the general-purpose registers to be grouped as register pairs. When used in this manner, the register pair can represent bit numbers. In some special cases the number in the register pair can be used as an address. The Flag Register. These flags are actually 1-bit flip-flops that 52 Chap.

Sign: If the most significant bit of the result of the operation has the value 1, this flag is set; otherwise it is reset. Parity: If the modulo 2 sum of the bits of the result'of the operation is 0, i. Carry: If the instruction resulted in a carry from addition , or a borrow from subtraction or a comparison out of the high-order bit, this flag is set; otherwise it is reset. Auxiliary carry: If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the auxiliary carry is set; otherwise it is reset.

This flag is affected by single precision additions, subtractions, increments, decrements, comparisons, and logical operations, but is principally used with additions and increments preceding a DAA Decimal Adjust Accumulator instruction.

In general, each instruction will affect all, some, or none of these flags. You can best understand the flags by studying several examples. Because the result is 0, the Z flag will be set. Ignoring the last four flags for the moment, the point you should note is that the Z flag is set when the result of an arithmetic or logical operation is 0. In this case the Z flag will be reset because the result is not zero. Because there were no carries generated, the AC and CY flags will also be reset.

The sign flag will be set because the most significant bit of the result is a 1. When the Sec. The steps in realizing this are: 1. The S flag will be reset because bit 7 is 0; the Z flag will be set because the result is 0; the AC flag will be set because a carry occurred from bit 3 to bit 4; the P flag will be set because the parity is even and the CY flag will be set because of the carry out of bit 7.

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Cancer 1 , 34—45 Montgomery, R. Maintenance of intratumoral androgens in metastatic prostate cancer: a mechanism for castration-resistant tumor growth.

Cancer Res. Locke, J. Androgen levels increase by intratumoral de novo steroidogenesis during progression of castration-resistant prostate cancer. Cai, C. Intratumoral de novo steroid synthesis activates androgen receptor in castration-resistant prostate cancer and is upregulated by treatment with CYP17A1 inhibitors.

Leon, C. Alterations in cholesterol regulation contribute to the production of intratumoral androgens during progression to castration-resistant prostate cancer in a mouse xenograft model.

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Arora, V. Glucocorticoid receptor confers resistance to antiandrogens by bypassing androgen receptor blockade. Cell , — Krycer, J. Cholesterol accumulation in prostate cancer: a classic observation from a modern perspective.

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Hulf, T. Epigenetic-induced repression of microRNA is associated with MED1 activation and a poorer prognosis in localized prostate cancer. Oncogene 32 , — Tucci, P. Loss of p63 and its microRNA target results in enhanced cell migration and metastasis in prostate cancer.

Natl Acad. USA , — Kneitz, B. Survival in patients with high-risk prostate cancer is predicted by miR, which regulates proliferation, apoptosis, and invasion of prostate cancer cells by inhibiting IRF2 and SOCS3.

Ambs, S. Du, Q. Cell 49 , — e Gregory, P. Cell Biol. Ryder, N. Specific inhibition of fungal sterol biosynthesis by SF , a new allylamine antimycotic agent. Agents Chemother. Gordon, J. Upregulation of scavenger receptor B1 is required for steroidogenic and nonsteroidogenic cholesterol metabolism in prostate cancer.

Chang, T. Cholesterol sensing, trafficking, and esterification. Annu Rev. Cell Dev. Mahoney, C. A chemical biology screen identifies a vulnerability of neuroendocrine cancer cells to SQLE inhibition. Padyana, A.

Structure and inhibition mechanism of the catalytic domain of human squalene epoxidase. Wu, T. Cancer 77 , — Korenchuk, S. VCaP, a cell-based model system of human prostate cancer.

In Vivo 15 , — Liu D. Garcia-Bermudez, J. Squalene accumulation in cholesterol auxotrophic lymphomas prevents oxidative cell death. Nature , — Azeem, W. An androgen response element driven reporter assay for the detection of androgen receptor activity in prostate cells. Slavin, M. Guidelines for the use of antifungal agents in the treatment of invasive Candida and mould infections. Labrecque, M. Molecular profiling stratifies diverse phenotypes of treatment-refractory metastatic castration-resistant prostate cancer.

Li, Q. Linking prostate cancer cell AR heterogeneity to distinct castration and enzalutamide responses. Bluemn, E. Androgen receptor pathway-independent prostate cancer is sustained through FGF signaling. Cancer Cell 32 , — e Kallio, H. Zhao, X. Glucocorticoids can promote androgen-independent growth of prostate cancer cells through a mutated androgen receptor. Ueda, T. Ligand-independent activation of the androgen receptor by interleukin-6 and the role of steroid receptor coactivator-1 in prostate cancer cells.

Gill, S. Cholesterol-dependent degradation of squalene monooxygenase, a control point in cholesterol synthesis beyond HMG-CoA reductase. Cell Metab. Brown, D. Squalene epoxidase is a bona fide oncogene by amplification with clinical relevance in breast cancer. Brown, M. The SREBP pathway: regulation of cholesterol metabolism by proteolysis of a membrane-bound transcription factor.

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