Why jtag is used

Upcoming Webinar. JTAG hardware debugger. Happy to serve you! Contact FAQ. For boards with low production volumes it has always been difficult to justify the cost of test fixture development. In these cases one alternative is flying probe testing; however the test cycle times tend to be high for this technology. This standard interface, which is the same for all JTAG enabled devices, means a generic set of test models can be used, and re-used, when building test systems.

JTAG is often already used as one step in production: programming. By also using JTAG for boundary scan test it is possible to reduce the number of steps and handling operations in the production process. Traditional test technologies require very large and expensive equipment. XJTAG also provides the capability to view both the physical location of a fault on the layout of the board and the logical design of the area of the circuit in which the fault exists on the schematic.

Traditional functional tests cannot be run if the board does not boot; simple faults on key peripherals, such as RAM or clocks, would be found using JTAG but would prevent functional tests from providing any diagnostic information.

Download as PDF. Testing BGA Connections. With boundary-scan such external probing is no longer needed. Thus boundary-scan was developed in a way that in case of miniaturization structural testing is still possible. In short: boundary-scan was developed to facilitate structural testing, also in case of miniaturization. The JTAG boundary-scan standard now provides many advantages over traditional systems. Examples of built-in resources in chips accessible through the JTAG interface are the boundary-scan register and the microcontroller debug logic.

Today, boundary-scan technology is probably the most popular and widely used design-for-test technique in the industry.

By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device.

These registers are connected in a dedicated path around the device's boundary hence the name , as shown in Figure 1. The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs. Figure 1: An integrated circuit with boundary scan. The boundary-scan cells can be configured to support external testing for interconnection between chips or internal testing for logic within the chip.

To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level. Test Access Port. The boundary-scan control signals, collectively referred to as the Test Access Port TAP , define a serial protocol for scan-based devices.

There are five pins:. The TAP controller manages the exchange of data and instructions. With the proper wiring, you can test multiple ICs or boards simultaneously. Test process. The standard test process for verifying a device or circuit board using boundary-scan technology is as follows:. Simple tests can find manufacturing defects such as unconnected pins, a missing device, an incorrect or rotated device on a circuit board, and even a failed or dead device. The primary advantage of boundary-scan technology is the ability to observe data at the device inputs and control the data at the outputs independently of the application logic.

Another benefit is the ability to reduce the number of overall test points required for device access. With boundary scan there are no physical test points. This can help lower board fabrication costs and increase package density.

Boundary scan provides a better set of diagnostics than other test techniques. Conventional techniques apply test vectors patterns to the inputs of the device and monitor the outputs.