Windows 2000 virtual memory manager

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Join Sign In. All rights reserved. Next, the page fault handler inside the operating system kernel will attempt to swap back this page to physical memory, possibly writing other memory contents to disk to make space. Usually, the system will apply a least-recently-used LRU schedule to decide which pages qualify to be swapped out. By now it should be clear why this procedure is sometimes referred to as demand paging: Physical memory contents are moved to the backup storage and back on software demand, based on statistics of the memory usage of the operating system and its applications.

The address indirection layer represented by the page-tables has two interesting implications. First, there is no predetermined relationship between the addresses used by a program and the addresses found on the physical address bus of the CPU chip.

If you know that a data structure of your application is located at the address, say, 0x, you still don't know anything about the physical address of your data unless you examine the page-table tree.

It is up to the operating system to decide what this address mapping looks like. Even more, the address translation currently in effect is unpredictable, in part because of the probabilistic nature of the paging mechanism.

Fortunately, knowledge of physical addresses isn't required in most application cases. This is something left for developers of hardware drivers. The second implication of paging is that the address space is not necessarily contiguous. Depending on the page-table contents, the 4-GB space can comprise large "holes" where neither physical nor backup memory is mapped.

If an application tries to read to or write from such an address, it will be aborted immediately by the system. Later in this chapter, I will show in detail how Windows spreads its available memory over the 4-GB address space. Along with higher clock frequencies, these newer models contain optimizations in other areas.

For example, the Pentium features a dual instruction pipeline that enables it to execute two operations at the same time, as long as these instructions don't depend on each other. For example, if instruction A modifies a register value, and the consecutive instruction B uses the modified value for a computation, B cannot be executed before A has finished.

But if instruction B involves a different register, the CPU can execute A and B simultaneously without adverse effects. This and other Pentium optimizations have opened a wide field for compiler optimization. In the context of i memory management, three sorts of addresses must be distinguished, termed logical, linear, and physical addresses in Intel's system programming manual for the Pentium Intel c.

This notation is borrowed from the old "segment:offset" style of specifying "far pointers" in Real-Mode. Linear addresses: Most applications and many kernel-mode drivers disregard virtual addresses. More precisely, they are just interested in the offset part of a virtual address, which is referred to as a linear address.

An address of this type assumes a default segmentation model, determined by the current values of the CPU's segment registers. Windows uses flat segmentation, with the CS, DS, ES, and SS registers pointing to the same linear address space; therefore, programs can safely assume that all code, data, and stack pointers can be cast among one another.

For example, a stack location can be cast to a data pointer at any time without concern about the values of the corresponding segment registers. Physical addresses: This address type is of interest only if the CPU works in paging mode. Basically, a physical address is the voltage pattern measurable at the address bus pins of the CPU chip. The operating system maps linear addresses to physical addresses by setting up page-tables.

The layout of the Windows page-tables, which has some very interesting properties for debugging software developers, will be discussed later in this chapter. The distinction between virtual and linear addresses is somewhat artificial, and some documentation uses both terms interchangeably.

I will do my best to use this nomenclature consistently. It is important to note that Windows assumes physical addresses to be 64 bits wide. This might seem odd on Intel i systems, which usually have a bit address bus. However, some Pentium systems can address more than 4 GB of physical memory.

Both types are defined in the DDK header file ntdef. Figure outlines the i memory segmentation model, showing the relationship between logical and linear addresses. For clarity, I have drawn the descriptor table and the segment as small, nonoverlapping boxes. However, this isn't a requirement. Actually, a bit operating system usually applies a segmentation layout as shown in Figure This so-called flat memory model is based on segments that span the entire 4-GB address space.

As a side effect, the descriptor table becomes part of the segment and can be accessed by all code that has sufficient access rights. Figure The memory model in Figure is adopted by Windows for the standard code, data, and stack segments, that is, all logical addresses that involve the CS, DS, ES, and SS segment registers.

The FS and GS segments are treated differently. GS is not used by Windows , and FS addresses special system data areas inside the linear address space. Therefore, its base address is greater than zero and its size is less than 4 GB. Interestingly, Windows maintains different FS segments in user-mode and kernel-mode. More on this topic follows later in this chapter. Flat 4-GB Memory Segmentation. In Figures and , the selector portion of the logical address is shown to point into a descriptor table determined by a register termed GDTR.

The first entry of the Global Descriptor Table GDT is reserved, and the corresponding selector called "null segment selector" is intended as an initial value for unused segment registers. Windows keeps its GDT at address 0x Windows uses only the first entries, restricting the GDT size to 1, bytes. Figure demonstrates the complex mechanism of linear-to-physical address translation applied by the i memory management unit if demand paging is enabled in 4-KB page mode.

Only the upper 20 bits are used for addressing. Therefore, the page-directory is always located on a page boundary. The remaining PDBR bits are either flags or reserved for future extensions. The page-directory occupies exactly one 4-KB page, structured as an array of 1, bit page-directory entries PDEs. Again, the. Address translation takes place by breaking a linear address into three parts: The upper 10 bits select a PDE out of the page-directory, the next lower 10 bits select a PTE out of the page-table addressed by the PDE, and, finally, the lower 12 bits specify an offset into the data page addressed by the PTE.

In the 4-KB paging scheme, the 4-GB linear address space is addressable by means of a double-layered indirection mechanism. In the worst case, 1,, PTEs are required to cover the entire range. Because each page-table holds 1, PTEs, this amounts to 1, page-tables, which is the number of PDEs the page-directory contains.

With the page-directory and each page-table consuming 4 KB, the maximum memory management overhead in this paging model is 4 KB plus 4 MB, or 4, KB. That's a reasonable price for a subdivision of the entire 4-GB space into 4-KB tiles that can be mapped to any linear address.

In 4-MB paging mode, things are much simpler because one indirection layer is eliminated, as shown in Figure Because no page-tables are used, this address is already the base address of a 4-MB data page. Consequently, the linear address now consists of two parts only: 10 bits for PDE selection and 22 offset bits. The 4-MB memory scheme requires no more than 4 KB overhead, because only the page-directory consumes additional memory. This is just enough to cover the entire 4-GB address space.

Thus, 4-MB pages have the advantage of keeping the memory management overhead low, but for the price of a more coarse addressing granularity. Both the 4-KB and 4-MB paging modes have advantages and disadvantages. Fortunately, operating system designers don't have to decide for one of them, but can run the CPU in mixed mode. The remaining linear address blocks are managed in 4-KB tiles. The operating system kernel is usually large and is always resident in memory, so storing it in several 4-KB pages would permanently use up valuable TLB space.

Note that all address translation steps are carried out in physical memory. Programs are loaded from Skip to main content. Windows Performance Guide by. Start your free trial. Chapter 6. Memory Management and Paging.